(1) Field of the Invention
The present invention relates to a standard cell system large scale integrated circuit, and is particularly concerned with a standard cell layout of an integrated circuit using a standard cell as design system.
(2) Description of the Prior Art
FIG. 3 shows a layout of conventional standard cells, wherein 1 denotes a power line, 2 denotes a clock line, 3 denotes a grounding conductor, 4 denotes a standard cell, and 5 denotes a wiring domain.
In such prior art device, only an element connection within the cell 4 is carried out internally, and a connection between the cells 4 is carried out in the wiring domain 5 outside the cells.
Then, the standard cell includes a basic logical element or composite gate such as inverter, NAND, NOR or the like and further D-FF, JK-FF, and for configuring a logical system, the aforementioned standard cells are arrayed and interconnected, however, a width of the wiring used for the interconnection is constant regardless of a species of signals.
The conventional standard cells are configured as described above, and according as an integrated circuit is designed in fine structure the intercell wiring becomes fine. However, in the case of clock line or the like which is abundant in fan-out number and wired on overall surface of a chip, the fine-arranged wiring may give rise to a problem on electron migration and resistance component. That is, if the wiring width is narrowed, a large current flows to the wiring due to charging and discharge where a load is heavy, the electron migration arises consequently, and a capacitance of the wiring decreases, however, since a capacitance of the load is large, the capacitance is not so decreasing as a whole and a resistance of the wiring increases accordingly to a disadvantage. Further, if the wiring width of a specific signal only is enlarged, the wiring becomes complicate generally, thus retarding automation of the wiring.